223 lines
7.0 KiB
C
223 lines
7.0 KiB
C
/**
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*******************************************************************************************************
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* @file fm33lg0xx_fl_cdif.h
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* @author FMSH Application Team
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* @brief Head file of CDIF FL Module
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*******************************************************************************************************
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* @attention
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*
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* Copyright (c) [2021] [Fudan Microelectronics]
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* THIS SOFTWARE is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*
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*******************************************************************************************************
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*/
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/* Define to prevent recursive inclusion---------------------------------------------------------------*/
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#ifndef __FM33LG0XX_FL_CDIF_H
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#define __FM33LG0XX_FL_CDIF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes -------------------------------------------------------------------------------------------*/
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#include "fm33lg0xx_fl_def.h"
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/** @addtogroup FM33LG0XX_FL_Driver
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* @{
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*/
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/** @defgroup CDIF CDIF
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* @brief CDIF FL driver
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* @{
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*/
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/* Exported types -------------------------------------------------------------------------------------*/
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/** @defgroup CDIF_FL_ES_INIT CDIF Exported Init structures
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* @{
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*/
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/**
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* @brief FL CDIF Init Sturcture definition
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*/
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/**
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* @}
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*/
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/* Exported constants ---------------------------------------------------------------------------------*/
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/** @defgroup CDIF_FL_Exported_Constants CDIF Exported Constants
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* @{
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*/
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#define CDIF_CR_INTF_IEN_Pos (1U)
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#define CDIF_CR_INTF_IEN_Msk (0x1U << CDIF_CR_INTF_IEN_Pos)
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#define CDIF_CR_INTF_IEN CDIF_CR_INTF_IEN_Msk
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#define CDIF_CR_INTF_OEN_Pos (0U)
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#define CDIF_CR_INTF_OEN_Msk (0x1U << CDIF_CR_INTF_OEN_Pos)
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#define CDIF_CR_INTF_OEN CDIF_CR_INTF_OEN_Msk
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#define CDIF_PRSC_PRSC_Pos (0U)
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#define CDIF_PRSC_PRSC_Msk (0x7U << CDIF_PRSC_PRSC_Pos)
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#define CDIF_PRSC_PRSC CDIF_PRSC_PRSC_Msk
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#define FL_CDIF_PSC_DIV1 (0x0U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV2 (0x1U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV4 (0x2U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV8 (0x3U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV16 (0x4U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV32 (0x5U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV64 (0x6U << CDIF_PRSC_PRSC_Pos)
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#define FL_CDIF_PSC_DIV128 (0x7U << CDIF_PRSC_PRSC_Pos)
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/**
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* @}
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*/
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/* Exported functions ---------------------------------------------------------------------------------*/
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/** @defgroup CDIF_FL_Exported_Functions CDIF Exported Functions
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* @{
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*/
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/**
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* @brief VAO To CPU input enable
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* @rmtoll CR INTF_IEN FL_CDIF_EnableVAOToCPU
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* @param CDIFx CDIF instance
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* @retval None
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*/
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__STATIC_INLINE void FL_CDIF_EnableVAOToCPU(CDIF_Type *CDIFx)
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{
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SET_BIT(CDIFx->CR, CDIF_CR_INTF_IEN_Msk);
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}
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/**
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* @brief Get VAO To CPU input enable status
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* @rmtoll CR INTF_IEN FL_CDIF_IsEnabledVAOToCPU
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* @param CDIFx CDIF instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t FL_CDIF_IsEnabledVAOToCPU(CDIF_Type *CDIFx)
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{
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return (uint32_t)(READ_BIT(CDIFx->CR, CDIF_CR_INTF_IEN_Msk) == CDIF_CR_INTF_IEN_Msk);
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}
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/**
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* @brief VAO To CPU input disable
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* @rmtoll CR INTF_IEN FL_CDIF_DisableVAOToCPU
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* @param CDIFx CDIF instance
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* @retval None
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*/
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__STATIC_INLINE void FL_CDIF_DisableVAOToCPU(CDIF_Type *CDIFx)
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{
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CLEAR_BIT(CDIFx->CR, CDIF_CR_INTF_IEN_Msk);
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}
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/**
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* @brief CPU To VAO enable
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* @rmtoll CR INTF_OEN FL_CDIF_EnableCPUToVAO
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* @param CDIFx CDIF instance
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* @retval None
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*/
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__STATIC_INLINE void FL_CDIF_EnableCPUToVAO(CDIF_Type *CDIFx)
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{
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SET_BIT(CDIFx->CR, CDIF_CR_INTF_OEN_Msk);
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}
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/**
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* @brief Get CPU To VAO output enable status
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* @rmtoll CR INTF_OEN FL_CDIF_IsEnabledCPUToVAO
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* @param CDIFx CDIF instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t FL_CDIF_IsEnabledCPUToVAO(CDIF_Type *CDIFx)
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{
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return (uint32_t)(READ_BIT(CDIFx->CR, CDIF_CR_INTF_OEN_Msk) == CDIF_CR_INTF_OEN_Msk);
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}
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/**
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* @brief CPU To VAO output disable
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* @rmtoll CR INTF_OEN FL_CDIF_DisableCPUToVAO
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* @param CDIFx CDIF instance
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* @retval None
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*/
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__STATIC_INLINE void FL_CDIF_DisableCPUToVAO(CDIF_Type *CDIFx)
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{
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CLEAR_BIT(CDIFx->CR, CDIF_CR_INTF_OEN_Msk);
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}
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/**
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* @brief Set CDIF prescaler
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* @rmtoll PRSC PRSC FL_CDIF_SetPrescaler
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* @param CDIFx CDIF instance
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* @param psc This parameter can be one of the following values:
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* @arg @ref FL_CDIF_PSC_DIV1
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* @arg @ref FL_CDIF_PSC_DIV2
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* @arg @ref FL_CDIF_PSC_DIV4
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* @arg @ref FL_CDIF_PSC_DIV8
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* @arg @ref FL_CDIF_PSC_DIV16
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* @arg @ref FL_CDIF_PSC_DIV32
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* @arg @ref FL_CDIF_PSC_DIV64
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* @arg @ref FL_CDIF_PSC_DIV128
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* @retval None
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*/
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__STATIC_INLINE void FL_CDIF_SetPrescaler(CDIF_Type *CDIFx, uint32_t psc)
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{
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MODIFY_REG(CDIFx->PRSC, CDIF_PRSC_PRSC_Msk, psc);
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}
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/**
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* @brief Get CDIF prescaler
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* @rmtoll PRSC PRSC FL_CDIF_GetPrescaler
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* @param CDIFx CDIF instance
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* @retval Returned value can be one of the following values:
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* @arg @ref FL_CDIF_PSC_DIV1
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* @arg @ref FL_CDIF_PSC_DIV2
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* @arg @ref FL_CDIF_PSC_DIV4
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* @arg @ref FL_CDIF_PSC_DIV8
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* @arg @ref FL_CDIF_PSC_DIV16
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* @arg @ref FL_CDIF_PSC_DIV32
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* @arg @ref FL_CDIF_PSC_DIV64
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* @arg @ref FL_CDIF_PSC_DIV128
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*/
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__STATIC_INLINE uint32_t FL_CDIF_GetPrescaler(CDIF_Type *CDIFx)
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{
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return (uint32_t)(READ_BIT(CDIFx->PRSC, CDIF_PRSC_PRSC_Msk));
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}
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/**
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* @}
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*/
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/** @defgroup CDIF_FL_EF_Init Initialization and de-initialization functions
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* @{
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FM33LG0XX_FL_CDIF_H*/
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/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-11*************************/
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/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
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