187 lines
6.9 KiB
C
187 lines
6.9 KiB
C
/**
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*******************************************************************************************************
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* @file fm33lg0xx_fl_pgl.c
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* @author FMSH Application Team
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* @brief Src file of PGL FL Module
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*******************************************************************************************************
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* @attention
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*
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* Copyright (c) [2021] [Fudan Microelectronics]
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* THIS SOFTWARE is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*
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*******************************************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "fm33lg0xx_fl.h"
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/** @addtogroup FM33LG0XX_FL_Driver
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* @{
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*/
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/** @addtogroup PGL
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* @{
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*/
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#ifdef FL_PGL_DRIVER_ENABLED
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup LUT_FL_Private_Macros
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* @{
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*/
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#define IS_FL_PGL_LUT_INSTANCE(INSTANCE) ((INSTANCE) == PGL)
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#define IS_FL_PGL_LUT_EDGE(__VALUE__) (((__VALUE__) == FL_PGL_LUT_EDGE_RISING)||\
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((__VALUE__) == FL_PGL_LUT_EDGE_FALLING)||\
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((__VALUE__) == FL_PGL_LUT_EDGE_BOTH)||\
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((__VALUE__) == FL_PGL_LUT_EDGE_NONE))
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#define IS_FL_PGL_LUT_OUT(__VALUE__) (((__VALUE__) == FL_PGL_LUT_OUTPUT_COMBINE_LOGIC)||\
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((__VALUE__) == FL_PGL_LUT_OUTPUT_SYNC_SAMPLING)||\
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((__VALUE__) == FL_PGL_LUT_OUTPUT_DIGITAL_FILTER))
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#define IS_FL_PGL_LUT_INPUTSEL(__VALUE__) (((__VALUE__) == FL_PGL_LUT_INPUT_GROUP0)||\
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((__VALUE__) == FL_PGL_LUT_INPUT_GROUP1)||\
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((__VALUE__) == FL_PGL_LUT_INPUT_GROUP2)||\
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((__VALUE__) == FL_PGL_LUT_INPUT_GROUP3)||\
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((__VALUE__) == FL_PGL_LUT_INPUT_DISABLE))
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup CRC_FL_EF_Init
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* @{
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*/
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/**
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* @brief 复位对应PGL寄存器.
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* @param PGLx
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* @retval ErrorStatus枚举值:
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* -FL_PASS 外设寄存器值恢复复位值
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* -FL_FAIL 未成功执行
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*/
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FL_ErrorStatus FL_PGL_DeInit(PGL_Type *PGLx)
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{
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assert_param(IS_FL_PGL_LUT_INSTANCE(PGLx));
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/* 使能外设复位 */
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FL_RMU_EnablePeripheralReset(RMU);
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/* 复位PGL外设寄存器 */
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FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_PGL);
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FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_PGL);
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/* 关闭外设总线时钟与工作时钟 */
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FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_PGL);
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/* 锁定外设复位 */
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FL_RMU_DisablePeripheralReset(RMU);
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return FL_PASS;
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}
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/**
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* @brief 根据 lutInit 的配置信息初始化对应外设入口地址的寄存器值
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* @param PGLx PGLx
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* @param lutInit 指向一个 @ref FL_PGL_LUT_InitTypeDef 结构体
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* 其中包含了外设的相关配置信息.
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* @retval ErrorStatus枚举值
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* -FL_FAIL 配置过程发生错误
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* -FL_PASS 配置成功
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*/
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FL_ErrorStatus FL_PGL_LUT_Init(PGL_Type *PGLx, uint32_t LUTx, FL_PGL_LUT_InitTypeDef *lutInit)
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{
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/* 入口参数检查 */
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assert_param(IS_FL_PGL_LUT_INSTANCE(PGLx));
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assert_param(IS_FL_PGL_LUT_EDGE(lutInit->edge));
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assert_param(IS_FL_PGL_LUT_OUT(lutInit->outMode));
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assert_param(IS_FL_PGL_LUT_INPUTSEL(lutInit->input3));
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assert_param(IS_FL_PGL_LUT_INPUTSEL(lutInit->input2));
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assert_param(IS_FL_PGL_LUT_INPUTSEL(lutInit->input1));
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assert_param(IS_FL_PGL_LUT_INPUTSEL(lutInit->input0));
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/* 总线时钟使能 */
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FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_PGL);
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/*有效边沿选择*/
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FL_PGL_SetLUTEffectiveEdge(PGLx, LUTx, lutInit->edge);
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/*输出模式选择*/
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FL_PGL_SetLUTOutputMode(PGLx, LUTx, lutInit->outMode);
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/*输入3选择*/
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if(lutInit->input3 == FL_PGL_LUT_INPUT_DISABLE)
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT3, FL_PGL_LUT_INPUT_GROUP0);
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FL_PGL_EnableLUTInputMask(PGLx, LUTx, FL_PGL_INPUT3); /* 屏蔽输入3通道 */
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}
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else
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT3, lutInit->input3);
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}
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/*输入2选择*/
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if(lutInit->input2 == FL_PGL_LUT_INPUT_DISABLE)
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT2, FL_PGL_LUT_INPUT_GROUP0);
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FL_PGL_EnableLUTInputMask(PGLx, LUTx, FL_PGL_INPUT2); /* 屏蔽输入2通道 */
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}
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else
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT2, lutInit->input2);
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}
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/*输入1选择*/
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if(lutInit->input1 == FL_PGL_LUT_INPUT_DISABLE)
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT1, FL_PGL_LUT_INPUT_GROUP0);
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FL_PGL_EnableLUTInputMask(PGLx, LUTx, FL_PGL_INPUT1); /* 屏蔽输入1通道 */
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}
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else
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT1, lutInit->input1);
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}
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/*输入0选择*/
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if(lutInit->input0 == FL_PGL_LUT_INPUT_DISABLE)
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT0, FL_PGL_LUT_INPUT_GROUP0);
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FL_PGL_EnableLUTInputMask(PGLx, LUTx, FL_PGL_INPUT0); /* 屏蔽输入0通道 */
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}
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else
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{
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FL_PGL_SetLUTInputSource(PGLx, LUTx, FL_PGL_INPUT0, lutInit->input0);
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}
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return FL_PASS;
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}
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/**
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* @brief 设置 PGL_InitStruct 为默认配置
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* @param PGL_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_PGL_LUT_InitTypeDef 结构体
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*
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* @retval None
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*/
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void FL_PGL_StructInit(FL_PGL_LUT_InitTypeDef *PGL_InitStruct)
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{
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PGL_InitStruct->edge = FL_PGL_LUT_EDGE_NONE;
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PGL_InitStruct->outMode = FL_PGL_LUT_OUTPUT_COMBINE_LOGIC;
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PGL_InitStruct->input3 = FL_PGL_LUT_INPUT_DISABLE;
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PGL_InitStruct->input2 = FL_PGL_LUT_INPUT_DISABLE;
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PGL_InitStruct->input1 = FL_PGL_LUT_INPUT_DISABLE;
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PGL_InitStruct->input0 = FL_PGL_LUT_INPUT_DISABLE;
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}
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/**
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* @}
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*/
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#endif /* FL_PGL_DRIVER_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
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