304 lines
8.7 KiB
C
304 lines
8.7 KiB
C
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/**************************************************************************//**
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* @file system_fm33lg0xx.c
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
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* Device FM33LG0XX
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* @version V2.0.0
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* @date 15. Mar 2021
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#include "system_fm33lg0xx.h"
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/* Clock Variable definitions ------------------------------------------------*/
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uint32_t XTLFClock = XTLF_DEFAULT_VALUE; /*!< External Low-freq Osc Clock Frequency (XTLF) */
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uint32_t XTHFClock = XTHF_DEFAULT_VALUE; /*!< External High-freq Osc Clock Frequency (XTHF) */
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uint32_t SystemCoreClock = HCLK_DEFAULT_VALUE; /*!< System Clock Frequency (Core Clock) */
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/* Clock functions -----------------------------------------------------------*/
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/**
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* @brief Retrieve the PLL clock frequency
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*
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* @retval PLL clock frequency
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*/
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static uint32_t SystemPLLClockUpdate(void)
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{
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uint32_t clock = 0;
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/* Acquire PLL clock source */
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switch ((CMU->PLLCR >> 1) & 0x1)
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{
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case 0:
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switch ((CMU->RCHFCR >> 16) & 0xFU)
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{
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case 1: /* 16MHz */
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clock = 16000000;
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break;
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case 2: /* 24MHz */
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clock = 24000000;
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break;
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case 3: /* 32MHz */
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clock = 32000000;
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break;
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case 0: /* 8MHz */
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default:
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clock = 8000000;
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break;
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}
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break;
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case 1:
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clock = XTHFClock;
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break;
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}
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/* Acquire PLL prescaler */
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switch ((CMU->PLLCR >> 0x4) & 0x7)
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{
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case 0: /* input divided by 1 */
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clock /= 1;
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break;
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case 1: /* input divided by 2 */
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clock /= 2;
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break;
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case 2: /* input divided by 4 */
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clock /= 4;
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break;
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case 3: /* input divided by 8 */
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clock /= 8;
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break;
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case 4: /* input divided by 12 */
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clock /= 12;
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break;
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case 5: /* input divided by 16 */
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clock /= 16;
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break;
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case 6: /* input divided by 24 */
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clock /= 24;
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break;
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case 7: /* input divided by 32 */
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clock /= 32;
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break;
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}
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/* Acquire PLL multiplier and calculate PLL frequency */
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clock = clock * (((CMU->PLLCR >> 16) & 0x7F) + 1);
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/* Acquire PLL output channel(PLLx1 or PLLx2) */
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if ((CMU->PLLCR >> 3) & 0x1)
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{
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clock *= 2;
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}
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return clock;
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}
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/**
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* @brief Update the core clock frequency variable: SystemCoreClock
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*
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*/
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void SystemCoreClockUpdate(void)
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{
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switch ((CMU->SYSCLKCR >> 0) & 0x7)
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{
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case 1: /* XTHF */
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SystemCoreClock = XTHFClock;
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break;
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case 2: /* PLL */
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SystemCoreClock = SystemPLLClockUpdate();
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break;
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case 4: /* RCLF */
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switch ((CMU->RCLFCR >> 16) & 0x3)
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{
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case 0: /* output divided by 1 */
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SystemCoreClock = 614400;
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break;
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case 1: /* output divided by 4 */
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SystemCoreClock = 153600;
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break;
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case 2: /* output divided by 8 */
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SystemCoreClock = 76800;
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break;
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case 3: /* output divided by 16 */
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SystemCoreClock = 38400;
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break;
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}
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break;
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case 5: /* XTLF */
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SystemCoreClock = XTLFClock;
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break;
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case 6: /* RCLP */
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SystemCoreClock = 32000;
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break;
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default:
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switch ((CMU->RCHFCR >> 16) & 0xf)
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{
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case 1: /* 16MHz */
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SystemCoreClock = 16000000;
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break;
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case 2: /* 24MHz */
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SystemCoreClock = 24000000;
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break;
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case 3: /* 32MHz */
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SystemCoreClock = 32000000;
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break;
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case 0: /* 8MHz */
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default:
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SystemCoreClock = 8000000;
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break;
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}
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break;
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}
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/* AHB Prescaler */
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switch((CMU->SYSCLKCR >> 8) & 0x7)
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{
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case 4: /* divide by 2 */
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SystemCoreClock /= 2;
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break;
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case 5: /* divide by 4 */
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SystemCoreClock /= 4;
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break;
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case 6: /* divide by 8 */
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SystemCoreClock /= 8;
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break;
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case 7: /* divide by 16 */
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SystemCoreClock /= 16;
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break;
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default: /* no division */
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break;
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}
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}
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/**
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit(void)
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{
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#if defined(USE_IWDT_ON_STARTUP)
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CMU->PCLKCR1 |= 0x20U; /* Enable IWDT Operation Clock */
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IWDT->CR = IWDT_OVERFLOW_PERIOD; /* Configure IWDT overflow period */
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IWDT->SERV = 0x12345A5AU; /* Enable IWDT */
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#endif
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/* Enable VREF Operation Clock */
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CMU->PCLKCR1 |= 0x1U << 12;
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/* Enable PAD Operation Clock */
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CMU->PCLKCR1 |= 0x1U << 7;
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#ifdef USE_LSCLK_AUTO_SWITCH
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/* Enable LSCLK auto switch */
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CMU->SYSCLKCR |= 0x8000000U;
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CMU->LSCLKSEL = 0x55U;
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#else
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/* Disable LSCLK auto switch */
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CMU->SYSCLKCR &= 0x7FFFFFFU;
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CMU->LSCLKSEL = 0x55U;
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#endif /* USE_LSCLK_AUTO_SWITCH */
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/* Keep timers running and disable IWDT && WWDT under debug mode */
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DBG->CR = 0x3U;
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#ifdef USE_DEBUG_UNDER_SLEEP
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/* Keep debug connnection under sleep mode */
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DBG->CR |= 0x1U << 16;
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#endif
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/* Load power trim value */
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PMU->ULPB_TR = ULPBG_TRIM;
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/* Load default clock trim value */
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CMU->RCHFTR = RCHF8M_TRIM;
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CMU->RCLFTR = RCLF_TRIM;
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CMU->RCLPTR = RCLP_TRIM;
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/* Enable SWD port pull up */
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GPIOD->PUEN |= 0x3U << 7;
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/*
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If BOR is disabled, power down will be monitored by PDR. This means VDD can
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be below the minimum operating voltage(1.65V) to V_PDR threshold without
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power down reset. To solve this, user should use SVD to monitor VDD voltage.
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When the VDD voltage drop below 1.65V, program can enter sleep.
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*/
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/* PDR Config enable 1.5v */
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RMU->PDRCR = 0x5;
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/* Disable BOR power down */
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RMU->BORCR = 0x01;
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/* Update System Core Clock */
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SystemCoreClockUpdate();
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#if defined(USE_IWDT_ON_STARTUP)
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IWDT->SERV = 0x12345A5AU; /* Feed IWDT */
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#endif
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// SCB->VTOR = 0x4000;
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}
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