166 lines
6.7 KiB
C
166 lines
6.7 KiB
C
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/**************************************************************************//**
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* @file system_fm33lg0xx.h
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
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* Device FM33LG0XX
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* @version V2.0.0
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* @date 15. Mar 2021
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef SYSTEM_FM33LC0XX_H
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#define SYSTEM_FM33LC0XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief CMSIS Device version number
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*/
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#define __FM33LG0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __FM33LG0xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __FM33LG0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:0] sub2 version */
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#define __FM33LG0xx_CMSIS_VERSION ((__FM33LG0xx_CMSIS_VERSION_MAIN << 24)\
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|(__FM33LG0xx_CMSIS_VERSION_SUB1 << 16)\
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|(__FM33LG0xx_CMSIS_VERSION_SUB2))
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/* Configurations ------------------------------------------------------------*/
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/**
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* @brief LSCLK auto switch
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* @note Comment the following line to enable LSCLK auto switch function.
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*/
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#define USE_LSCLK_AUTO_SWITCH
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/**
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* @brief Keep debug connection under sleep mode
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* @note Uncomment the following line to debug under sleep mode
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*/
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/* #define USE_DEBUG_UNDER_SLEEP */
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/**
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* @brief Open IWDT on program startup
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* @note Uncomment the following line to use IWDT on startup. User can modify
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* the IWDT_OVERFLOW_PERIOD to change the IDWT overflow period.
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*/
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/* #define USE_IWDT_ON_STARTUP */
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#ifdef USE_IWDT_ON_STARTUP
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/*
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Valid value of IWDT_OVERFLOW_PERIOD:
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- 0x0: 125ms
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- 0x1: 250ms
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- 0x2: 500ms
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- 0x3: 1s
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- 0x4: 2s
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- 0x5: 4s
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- 0x6: 8s
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- 0x7: 16s
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*/
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#define IWDT_OVERFLOW_PERIOD 0x7
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#endif /* USE_IWDT_ON_STARTUP */
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/* Includes ------------------------------------------------------------------*/
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#include <stdint.h>
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/* Device Includes -----------------------------------------------------------*/
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#include "fm33lg0xx.h"
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/* Trim Values ---------------------------------------------------------------*/
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/* Validate Function */
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#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
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((((_N_VALUE_ >> 16) & 0xFFFFU) == \
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(~(_N_VALUE_) & 0xFFFFU)) ? (_N_VALUE_) : (_T_VALUE_))
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/* Trim Values Address */
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#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40U) /* RC8M trim value */
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#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3CU) /* RC16M trim value */
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#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38U) /* RC24M trim value */
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#define RCHF32M_LDT_TRIM (*(uint32_t *)0x1FFFFB34U) /* RC32M trim value */
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#define RCLF_LDT_TRIM (*(uint32_t *)0x1FFFFB44U) /* RCLF trim value */
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#define RCLP_LDT_TRIM (*(uint32_t *)0x1FFFFB20U) /* RCLP trim value */
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#define ULPBG_LDT_TRIM (*(uint32_t *)0x1FFFFA98U) /* ULPBG trim value */
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/* Trim Values */
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#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x80U) & 0xFFU)
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#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x80U) & 0xFFU)
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#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x80U) & 0xFFU)
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#define RCHF32M_TRIM (LDT_CHECK(RCHF32M_LDT_TRIM, 0x80U) & 0xFFU)
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#define RCLF_TRIM (LDT_CHECK(RCLF_LDT_TRIM, 0x80U) & 0xFFU)
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#define RCLP_TRIM (LDT_CHECK(RCLP_LDT_TRIM, 0x80U) & 0xFFU)
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#define ULPBG_TRIM (LDT_CHECK(ULPBG_LDT_TRIM, 0x10U) & 0x1FU)
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/* Default Clock Frequency Values --------------------------------------------*/
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#define XTHF_DEFAULT_VALUE ((uint32_t)8000000U) /*!< Default value of XTHF in Hz */
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#define XTLF_DEFAULT_VALUE ((uint32_t)32768U) /*!< Default value of XTLF in Hz */
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/* Default system core clock value */
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#define HCLK_DEFAULT_VALUE ((uint32_t)8000000U)
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/* Exported Clock Frequency Variables --------------------------------------- */
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/*
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- [SystemCoreClock] holds the value of CPU operation clock freqency, and is initialized
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to HCLK_DEFAULT_VALUE;
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- [XTLFClock] holds the value of external low-frequency oscillator(XTLF),
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and is initialized to XTLF_DEFAULT_VALUE;
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- [XTHFClock] holds the value of external high_frequency oscillator(XTHF),
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and is initialized to XTHF_DEFAULT_VALUE;
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NOTE: If users are using these two external oscillators, they should modify the
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value of XTLFClock and XTHFClock to the correct value, and call the SystemCoreClockUpdate()
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to update the SystemCoreClock variable, otherwise those codes which rely on
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the SystemCoreClock variable will fail to run.
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*/
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extern uint32_t XTLFClock; /*!< External Low-freq Osc Clock Frequency (XTLF) */
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extern uint32_t XTHFClock; /*!< External High-freq Osc Clock Frequency (XTHF) */
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit(void);
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/**
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* @brief Updates the SystemCoreClock with current core Clock
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* retrieved from cpu registers.
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*/
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void SystemCoreClockUpdate(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYSTEM_FM33LG0XX_H */
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